Adaptive power routing and shield sharing to reduce shield count

ABSTRACT

Described herein are two techniques referred to as “Adaptive Power Routing” and “Shield Sharing To Reduce Shield Count,” that allow power routing and signal routing to be integrated in a manner that provides more efficient and compact layout of design blocks as compared to traditional techniques. Adaptive power routing refers to completion of power routing to be postponed to the signal routing phase, at which time signal shielding requirements are also used to complete the power routing along with predefined power delivery constraints. Shield sharing optimization refers to the more efficient use of previously routed power lines and to the insertion of a reduced number of additional power lines so as to satisfy both shielding requirements and power supply requirements in a gridless environment. These two techniques allow routing in highly congested regions containing performance-critical and/or noise-sensitive signals to be manufactured using less die area than would be required with traditional routing methodologies and algorithms.

FIELD

[0001] The invention relates to integrated circuit layout. Moreparticularly, the invention relates to area-efficient techniques forplacing and routing signal nets and power and ground supply lines in anintegrated device layout to control electrical cross-coupling betweenadjacent signal lines.

BACKGROUND

[0002] As processes for manufacturing integrated devices allow minimumline sizes to decrease, the potential for interconnect noise due toswitching cross-coupling capacitance increases. This switchingcross-coupling capacitance increases the difficulty of converging highperformance circuits by widening the transition windows of signals toaccount for unpredictable transition states of neighboring signals, aswell as by causing failures. Convergence refers to conditions underwhich all timing requirements are met.

[0003] In view of this situation, designers often attempt to reduceswitching cross-coupling capacitance by shielding sensitive signal netsusing power supply (Vcc) or ground (Vss) lines. The set of linesproviding any combination of a positive supply voltage, a negativesupply voltage and/or ground are referred to herein as “power lines.”Shielding can be accomplished by placing sensitive signal nets adjacentto pre-existing power lines or by adding power lines adjacent to thesensitive signal lines for the purpose of shielding.

[0004] With the effects of switching cross-coupling capacitanceincreasing with each generation of integrated device manufacturingprocesses, the proportion of signals requiring shielding, andconsequently the area used by the shields also increases. Because designblocks layouts are often wire-limited, an increase in the number ofpower lines required solely for shielding increases the die arearequired to manufacture the integrated device.

[0005] Furthermore, detailed shielding requirements are available onlyat late stages in the design process, at which time the die areaavailable to lay out each converged design block may already have beenallocated. In such a scenario, if the layout of a converged design blockcannot be carried out in its planned area, extensive delays can beincurred due to redesign of the surrounding design blocks.

[0006] L. He, “Simultaneous Shield Insertion and Net Ordering forCapacitive and Inductive Coupling Minimization,” Proc. ISPD'00(hereinafter “the He Paper”) discloses a technique for integratedshielding and signal net ordering. However, the He Paper focuses onsignal net ordering and shield insertion primarily for inductive noiseunder a simplistic model and is not well suited to layouts containingmay prerouted signal nets and shields, which is common. Furthermore, theHe Paper does not address either shield sharing or power gridperturbation.

BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The invention is illustrated by way of example, and not by way oflimitation, in the figures of the accompanying drawings in which likereference numerals refer to similar elements.

[0008]FIG. 1 is one embodiment of a flow diagram for power supply andsignal net routing.

[0009]FIG. 2 illustrates a block diagram of one embodiment of anelectronic system.

[0010]FIG. 3a illustrates a sample routing of signal nets and powerlines using traditional routing methodologies.

[0011]FIG. 3b illustrates the routing of the signal nets and of powerlines using adaptive power routing and shield sharing to reduce shieldcount.

[0012]FIG. 4 illustrates adaptive power routing in an integrated circuitdesign block.

DETAILED DESCRIPTION

[0013] Techniques for power supply routing in an integrated device suchthat the power supply lines are used to shield signal lines aredescribed. In the following description, for purposes of explanation,numerous specific details are set forth in order to provide a thoroughunderstanding of the invention. It will be apparent, however, to oneskilled in the art that the invention can be practiced without thesespecific details. In other instances, structures and devices are shownin block diagram form in order to avoid obscuring the invention.

[0014] Reference in the specification to “one embodiment” or “anembodiment” means that a particular feature, structure, orcharacteristic described in connection with the embodiment is includedin at least one embodiment of the invention. The appearances of thephrase “in one embodiment” in various places in the specification arenot necessarily all referring to the same embodiment.

[0015] It has been noted by design engineers in the field of integratedcircuit (IC) design that process migration often results in an increasein interconnect noise induced due to switching cross-capacitance, whichresults in increasing difficulty in designing functional circuits.Furthermore, switching cross-capacitance increases the difficulty ofconverging high performance circuits by widening the transition windowsof signals to account for unpredictable transition states of neighboringsignals.

[0016] In view of these factors, circuit designers attempt to minimizeswitching cross-capacitance by shielding sensitive signal nets usingpower supply (Vcc) and ground (Vss) lines (collectively “power lines”).As described herein, by integrating two traditionally disjoint phases ofthe layout process (viz., power routing and signal routing) in a waythat satisfies both shielding and power delivery integrity constrainswhile using a reduced number of power lines, the disadvantages oftraditional technologies can be overcome.

[0017] Described herein are two techniques referred to as “AdaptivePower Routing” and “Shield Sharing To Reduce Shield Count,” that allowpower routing and signal routing to be integrated in a manner to providemore efficient and compact layout of design blocks as compared totraditional techniques. Adaptive power routing refers to a techniquethat allows the completion of power routing to be postponed to thesignal routing phase, at which time signal shielding requirements arealso used to complete the power routing along with predefined powerdelivery constraints. The phrase “design block” refers to a collectionof circuit elements.

[0018] Shield sharing to reduce shield count refers to a technique touse previously routed power lines more efficiently and to insert areduced number of additional power lines so as to satisfy the shieldingrequirements of delay- and/or noise-sensitive signals. In oneembodiment, this can be accomplished efficiently in a gridless routingenvironment. This technique along with adaptive power routing allowsrouting in regions containing sensitive signals (e.g., dynamic logiccircuits) to be completed using less die area than would be requiredwith traditional routing methodologies and algorithms.

[0019] In general, unlike traditional routing methodologies where powerrouting is completed prior to signal routing, the technique describedherein results in a postponement of detailed power routing until laterin the layout flow by integrating the detailed power routing adaptivelyinto signal routing as described with respect to FIG. 1, which is a flowdiagram of one embodiment of a technique for power supply and signal netrouting. If a local region has insufficient shields subsequent to signalrouting, additional power lines can be inserted as part of the adaptivepower routing in order to maintain power delivery integrity.

[0020] Prior to layout, the timing and noise characteristics of thecircuit are analyzed to determine wire and device sizes as well as theshielding requirements for signal nets, 100. Signal nets are ordered bythe degree of freedom in their placement and by their shieldingrequirements, 110. In one embodiment, the degree of freedom of a signalnet is determined by the number of available tracks within thecumulative span of its driver(s) and by the number of shields requiredby the signal net.

[0021] In one embodiment, the most constrained signal net is routedgridlessly along with any associated shields, 120. Using the orderingdescribed above, each signal net is placed so as to reuse previouslyrouted shields as much as possible. During this process, 125, theordering of the signal nets is dynamically updated, 110, with the mostconstrained remaining signal net and shields being routed at each stage,120. The reordering and placement of signal nets and associated shields,if any, is repeated until all signal nets are routed, 130. At thisstage, the polarity of the shields is unassigned.

[0022] The polarity of the existing power lines as well as existing andnewly inserted shield lines is assigned in a manner to satisfy the powerpitch, 140. The power pitch is the maximum allowable distance betweenadjacent power lines of opposite polarities for a particularmanufacturing process. The power pitch is a predetermined value that isknown prior to layout of signal nets and power lines. If assigning ofpolarities to the shield lines does not provide enough power lines tosatisfy the power pitch, new power lines are inserted, 150.

[0023] In one embodiment, the region as defined by a previous power lineand the routing track one power pitch beyond that power line isiteratively searched for shields starting from the far end of the regionand moving toward the existing power line. If a shield is found, thatshield is treated as part of the power grid and assigned a polarityopposite of the previous power line. Thus, the separation between theexisting power line and the new power line is no greater than the powerpitch in this case, thus ensuring power delivery integrity. Moresignificantly, no new power line needs to be added in this case incontrast to traditional routing methodologies.

[0024] A new power line is explicitly added, 160, only if no shieldexists within the power pitch region. Even in this case, the techniquesdescribed herein provide more efficient routing completion thantraditional techniques by allowing the power lines to be assigned to anyunused track over a region of equal width to the power pitch. Incontrast, traditional non-adaptive power routing requires that the powerline be added to a considerably smaller region. Thus, the number ofpower lines in the layout is less than a corresponding layout usingtraditional methodologies, which results in a more compact layout.

[0025] The shields that have not had polarities assigned are assigned,170. In one embodiment, these shields are assigned Vss; however, theseshields can also be assigned Vcc.

[0026]FIG. 4 illustrates an integrated circuit design block. Integrateddesign block 400 includes multiple signal nets and their associatedshield lines that are not illustrated for reasons of simplicity ofdescription. In one embodiment, after signal nets and associated shieldlines are routed, a power grid is extracted from the existing shieldlines as much as possible with additional power lines being explicitlyadded only where necessary to satisfy power delivery requirements.

[0027] In one embodiment, extraction of a power grid from shield linesplaced in integrated circuit design block 400 starts at boundary 460.Any boundary can be used as a starting point and non-boundary startingpoints can also be used. A first region is defined with respect toboundary 460. In one embodiment, the first region is one half of a powerpitch (λ/2); however, the first region can be defined in another manner.

[0028] The first region is searched starting at boundary (dashed line)420 opposite starting boundary 460. The dashed lines of FIG. 4 are forillustration purposes only and are not part of the integrated circuitdesign block layout. The tracks of the first region are searched for ashield line that is the greatest distance from boundary 460. In theexample of FIG. 4, shield line 410 is the shield line within the firstregion that is the greatest distance from boundary 460. Shield line 410is used as part of the power grid and assigned a polarity (either Vcc orVss).

[0029] A second region of design block 400 is defined based onshield/power line 410 as the starting boundary. In one embodiment,regions beyond the first region are defined as a power pitch (λ) or theboundary of the design block, whichever is smaller. Thus, the secondregion is defined by shield/power line 410 and dashed line 440.

[0030] The second region is searched from dashed line 440 towardshield/power line 410 to find a shield line that is the greatestdistance from shield/power line 410, if any. In the example of FIG. 4,shield line 430 is the shield line in the second region that is thegreatest distance from shield/power line 410. Shield line 430 is used aspart of the power grid and assigned a polarity opposite of shield/powerline 410.

[0031] A third region of design block 400 is defined based onshield/power line 430 as the starting boundary. Using a power pitchdistance, the third region is defined by shield/power line 430 anddashed line 450. As described above, the third region is searched fromdashed line 450 to shield/power line 430 to find a shield line that isthe greatest distance from shield/power line 430. In the example of FIG.4, no shield line exists in the third region. If no usable shield lineexists, a power line (not shown in FIG. 4) is explicitly added to designblock 400 in a vacant track in the third region that is farthest fromshield/power line 430 in order to satisfy power delivery requirements.

[0032] In one embodiment, the technique described herein is implementedas sequences of instructions executed by an electronic system. Thesequences of instructions can be stored by the electronic device or theinstructions can be received by the electronic device (e.g., via anetwork connection). FIG. 2 is a block diagram of one embodiment of anelectronic system. The electronic system illustrated in FIG. 2 isintended to represent a range of electronic systems, for example,computer systems, network access devices, etc. Alternative electronicsystems can include more, fewer and/or different components.

[0033] Electronic system 200 includes bus 201 or other communicationdevice to communicate information, and processor 202 coupled to bus 201to process information. While electronic system 200 is illustrated witha single processor, electronic system 200 can include multipleprocessors and/or co-processors. Electronic system 200 further includesrandom access memory (RAM) or other dynamic storage device 204 (referredto as memory), coupled to bus 201 to store information and instructionsto be executed by processor 202. Memory 204 also can be used to storetemporary variables or other intermediate information during executionof instructions by processor 202.

[0034] Electronic system 200 also includes read only memory (ROM) and/orother static storage device 206 coupled to bus 201 to store staticinformation and instructions for processor 202. Data storage device 207is coupled to bus 201 to store information and instructions. Datastorage device 207 such as a magnetic disk or optical disc andcorresponding drive can be coupled to electronic system 200.

[0035] Electronic system 200 can also be coupled via bus 201 to displaydevice 221, such as a cathode ray tube (CRT) or liquid crystal display(LCD), to display information to a computer user. Alphanumeric inputdevice 222, including alphanumeric and other keys, is typically coupledto bus 201 to communicate information and command selections toprocessor 202. Another type of user input device is cursor control 223,such as a mouse, a trackball, or cursor direction keys to communicatedirection information and command selections to processor 202 and tocontrol cursor movement on display 221. Electronic system 200 furtherincludes network interface 230 to provide access to a network, such as alocal area network.

[0036] Instructions are provided to memory from a storage device, suchas magnetic disk, a read-only memory (ROM) integrated circuit, CD-ROM,DVD, via a remote connection (e.g., over a network via network interface230) that is either wired or wireless providing access to one or moreelectronically-accessible media, etc. In alternative embodiments,hard-wired circuitry can be used in place of or in combination withsoftware instructions. Thus, execution of sequences of instructions isnot limited to any specific combination of hardware circuitry andsoftware instructions.

[0037] An electronically-accessible medium includes any mechanism thatprovides (i.e., stores and/or transmits) content (e.g., computerexecutable instructions) in a form readable by an electronic device(e.g., a computer, a personal digital assistant, a design blockulartelephone). For example, a machine-accessible medium includes read onlymemory (ROM); random access memory (RAM); magnetic disk storage media;optical storage media; flash memory devices; electrical, optical,acoustical or other form of propagated signals (e.g., carrier waves,infrared signals, digital signals); etc.

[0038] To illustrate the results of signal net routing and power routingusing the techniques described herein, FIGS. 3a and 3 b illustratesignal net routing and power routing using traditional techniques andusing adaptive power routing and shield sharing, respectively. In FIGS.3a and 3 b, the solid lines represent signal nets (labeled Ni), with thenumbers in parenthesis indicating the number of shields required by theassociated signal nets. In FIG. 3a, the dotted lines represent the powerlines, with the heavy dotted lines representing the power tracksassigned during the power routing phase prior to signal routing.

[0039] Traditional routing methodologies tend to produce traceassignments similar to FIG. 3a because these methodologies do not orderthe signal nets according to shielding requirements to reduce theoverall number of shields required. Thus, once signal net N1 has beenrouted, signal net N2 is routed in the next available track along withany required shields.

[0040] In contrast, the technique described herein results in a layoutlike the one in FIG. 3b. Using this methodology, the signal nets to berouted in this region are reordered so as to share as many shields aspossible (e.g., between signal nets N2 and N4). As a result, additionalpower lines are often not required (as in the lower portion of FIG. 3b)because power can be adequately delivered through the shields that havebeen routed during signal net routing.

[0041] However, because signal routing and the associated shieldplacement does not provide adequate power to the top portion of thelayout of FIG. 3b, an additional power track as represented by the heavydotted line in FIG. 3b is assigned to be Vcc or Vss, with polarityassigned as needed, to meet power delivery constraints.

[0042] As can be seen from FIGS. 3a and 3 b, the layout produced usingthe adaptive power routing and shield sharing techniques results in amore compact layout than that using traditional techniques. Adaptivepower routing and shield sharing thus satisfy signal routing, signalshielding and power delivery constraints in a more efficient manner thantraditional techniques.

[0043] The signal net and power delivery routing techniques describedherein are most effective when used on middle metal layers. Thetechnique is less effective when used on upper metal layers where longrange matching of power networks is a stringent requirement. However, inlayers where power networks of adjacent design blocks are generally notrequired to match exactly because of dense connections through the upperlayers, the techniques described herein are more effective.

[0044] In the foregoing specification, the invention has been describedwith reference to specific embodiments thereof. It will, however, beevident that various modifications and changes can be made theretowithout departing from the broader spirit and scope of the invention.The specification and drawings are, accordingly, to be regarded in anillustrative rather than a restrictive sense.

What is claimed is:
 1. A method comprising: determining a priority for aplacement of a set of signal lines in a gridless layout of an integrateddevice; placing a most constrained signal line from the set of signallines, wherein the placement is determined based on previously routedsignal lines, previously routed power lines and/or shieldingrequirements; and re-determining the priority of the remaining signallines in the set of signal lines.
 2. The method of claim 1 whereindetermining an order for placement of signal lines comprises orderingthe signal lines based on one or more of: geometric constraints,shielding constraints and previously routed signal and/or power lines.3. The method of claim 2 wherein placing the most constrained signalline from the set of signal lines further comprises: placing theselected signal line in a first available track, possibly adjacent to apreviously placed shield line and/or a previously placed power line; andplacing a shield line, if necessary, adjacent to the placed selectedsignal line according to a predetermined policy of placing shieldinglines without an associated polarity.
 4. The method of claim 3 whereinplacing the shield, if necessary, adjacent to the placed selected signalline according to a predetermined policy comprises: placing a shieldline adjacent to the placed selected signal line if previously placedpower and/or shielding lines are not available to provide shielding tothe selected signal line; analyzing unplaced signal lines from the setof signal lines to determine whether any of the unplaced signal linesrequires additional shielding; and placing the shield line such that anunplaced signal line requiring shielding can be placed adjacent to theshield line, if possible.
 5. The method of claim 3 further comprisingassigning polarities to the shielding lines placed without an associatedpolarity such that the shielding lines and/or any previously placedpower lines satisfy a predetermined power pitch.
 6. The method of claim5 wherein assigning polarities to the shielding lines comprisesassigning the shielding lines to be either a positive voltage supply,ground, or a negative voltage supply.
 7. An integrated circuitmanufactured according to the method of claim
 1. 8. An integratedcircuit manufactured according to the method of claim
 4. 9. Anintegrated circuit manufactured according to the method of claim
 6. 10.A method of providing adequate shielding to a congested design block ofan integrated circuit layout containing critical signal nets, the methodcomprising: placing signal lines for the design block according to apredetermined policy, wherein placement of the signal lines may resultin movement of the previously placed power lines, and further whereinplacement of the signal lines results in placement of shielding lineswithin the design block, the shielding lines placed without anassociated polarity and adjacent to one or more critical signal lines;providing a polarity to the shielding lines such that the combination ofthe power lines and the shielding lines satisfy a predetermined powerpitch.
 11. The method of claim 10 wherein the critical signal netscomprise noise critical signal nets.
 12. The method of claim 10 whereinthe critical signal nets comprise performance critical signal nets. 13.The method of claim 10 wherein placing signal lines for the design blockaccording to a predetermined policy comprises: determining a priorityfor a placement of a set of signal lines in a gridless layout of anintegrated device; placing a most constrained signal line from the setof signal lines, wherein the placement is determined based on previouslyrouted signal lines, previously routed power lines and shieldingrequirements; and re-determining the priority of the remaining signallines in the set of signal lines.
 14. An integrated circuit manufacturedaccording to the method of claim
 10. 15. A method comprising: routingsignal lines for a design block of an integrated circuit; placingshielding lines within the design block as necessary based on sensitivesignal line requirements; and placing additional power lines asnecessary to satisfy power grid requirements.
 16. The method of claim 15wherein the placing the shielding lines within the design block asnecessary comprises placing the shielding lines without an associatedpolarity.
 17. The method of claim 16 further comprising assigningpolarity to the shielding lines after the signal lines and the shieldinglines have been placed, the polarities being assigned such that theshielding lines and power lines satisfy a predetermined power gridcondition.
 18. The method of claim 15 wherein routing signal lines for adesign block of an integrated circuit comprises dynamic signal linereordering.
 19. The method of claim 18 wherein the dynamic signalreordering is based on one or more of: geometric constraints, shieldingconstraints and previously routed signal and/or power lines.
 20. Anintegrated circuit manufactured according to the method of claim
 15. 21.An article comprising a storage medium accessible by an electronicdevice, the storage medium to store instructions that, when executed byone or more processors, cause the one or more processors to: determine apriority for a placement of a set of signal lines in a gridless layoutof an integrated device; place a most constrained signal line from theset of signal lines, wherein the placement is determined based onpreviously routed signal lines, previously routed power lines and/orshielding requirements; and re-determine the priority of the remainingsignal lines in the set of signal lines.
 22. The article of claim 21wherein the instructions that cause the one or more processors todetermine an order for placement of signal lines comprises instructionsthat, when executed by the one or more processors, cause the one or moreprocessors to order the signal lines based on one or more of: geometricconstraints, shielding constraints and previously routed signal and/orpower lines.
 23. The article of claim 21 wherein the instructions thatcause the one or more processors to place the most constrained signalline from the set of signal lines further comprises instruction that,when executed by the one or more processors, cause the one or moreprocessors to: place a selected signal line in a first available track,possibly adjacent to a previously placed shield or a previously placedpower line; and place a shield line, if necessary, adjacent to theplaced selected signal line according to a predetermined policy ofplacing shielding lines without an associated polarity.
 24. The articleof claim 23 wherein the instructions that cause the one or moreprocessors to place the shield, if necessary, adjacent to the placedselected signal line according to a predetermined policy comprisesinstructions that, when executed by the one or more processors, causethe one or more processors to: place a shield line adjacent to theplaced selected signal line if previously placed power and/or shieldinglines are not available to provide shielding to the selected signalline; analyze unplaced signal lines from the set of signal lines todetermine whether any of the unplaced signal lines requires additionalshielding; and place the shield line such that an unplaced signal linerequiring shielding can be placed adjacent to the shield line, ifpossible.
 25. The article of claim 24 further comprising instructionsthat, when executed by the one or more processors, cause the one or moreprocessors assign polarities to the shielding lines placed without anassociated polarity such that the shielding lines and any previouslyplaced power lines satisfy a predetermined power pitch.
 26. The articleof claim 25 wherein the instructions that cause the one or moreprocessors to assign polarities to the shielding lines comprisesinstructions that, when executed by the one or more processors, causethe one or more processors to assign the shielding lines to be either apositive voltage supply, ground, or a negative voltage supply.
 27. Anarticle comprising an electronically accessible medium to storeinstructions to providing adequate shielding to a congested design blockof an integrated circuit layout containing critical signal nets, theinstructions, when executed by one or more processors, cause the one ormore processors to: place signal lines for the design block according toa predetermined policy, wherein placement of the signal lines may resultin movement of the previously placed power lines, and further whereinplacement of the signal lines results in placement of shielding lineswithin the design block, the shielding lines placed without anassociated polarity and adjacent to one or more critical signal lines;and provide a polarity to the shielding lines such that the combinationof the power lines and the shielding lines satisfy a predetermined powerpitch.
 28. The article of claim 27 wherein the instructions that causethe one or more processors to place signal lines for the design blockaccording to a predetermined policy comprises instructions that, whenexecuted by the one or more processors, cause the one or more processorsto: determine a priority for a placement of a set of signal lines in agridless layout of an integrated device; place a most constrained signalline from the set of signal lines, wherein the placement is determinedbased on previously routed signal lines, previously routed power linesand shielding requirements; and reorder the priority of the remainingsignal lines in the set of signal lines.
 29. An article comprising astorage medium accessible by an electronic device, the storage medium tostore instructions that, when executed by one or more processors, causethe one or more processors to: route signal lines for a design block ofan integrated circuit; place shielding lines within the design block asnecessary based on sensitive signal line requirements; and placeadditional power lines as necessary to satisfy power grid requirements.30. The article of claim 29 wherein the placing the shielding lineswithin the design block as necessary comprises placing the shieldinglines without an associated polarity.
 31. The article of claim 30further comprising instructions that, when executed by the one or moreprocessors, cause the one or more processors to assign polarity to theshielding lines after the signal lines and the shielding lines have beenplaced, the polarities being assigned such that the shielding lines andpower lines satisfy a predetermined power grid condition.
 32. Thearticle of claim 29 wherein routing signal lines for a design block ofan integrated circuit comprises dynamic signal line reordering.
 33. Thearticle of claim 32 wherein the dynamic signal reordering is based onone or more of. geometric constraints, shielding constraints andpreviously routed signal and/or power lines.
 34. A method comprising:routing signal lines and associated shield lines for an integratedcircuit layout, wherein power lines are not explicitly routed prior torouting the signal lines; identifying one or more shield lines for useas power lines; and adding additional power lines to the layoutexplicitly if the shield lines identified for use as power lines do notmeet predetermined power delivery requirements.
 35. The method of claim34 wherein routing signal lines and associated shield lines comprisesdynamically determining an order for placement based on geometricconstraints, shielding constraints and/or previously routed signaland/or power lines.
 36. The method of claim 34 wherein routing signallines and associated shield lines comprises: placing a selected signalline in a first available track, possibly adjacent to a previouslyplaced shield line and/or a previously placed power line; and placing ashield line, if necessary, adjacent to the placed selected signal lineaccording to a predetermined policy of placing shield lines without anassociated polarity.
 37. The method of claim 34 wherein identifying oneor more shield lines for use as power lines comprises: searching a firstregion with respect to a first layout boundary for a shield line;causing an identified shield line in first region, if any, to be a powerline by assigning a polarity to the identified shield line; inserting apower line in the first region if a shield line is not identified withinthe first region.
 38. The method of claim 37 further comprising:identifying a second region a predetermined distance beyond the firstregion; searching the second region for a shield line; causing anidentified shield line in the second region, if any, to be a power lineby assigning a polarity to the identified shield line, wherein thepolarity is opposite of the identified shield line of the first region;inserting a power line in the second region if a shield line is notidentified within the second region.
 39. The method of claim 38 whereinthe predetermined distance corresponds to a power pitch distance. 40.The method of claim 38 wherein searching the second region for a shieldline comprises identifying a shield line a greatest distance from thefirst region.
 41. An integrated circuit manufactured according to themethod of claim
 34. 42. An integrated circuit manufactured according tothe method of claim
 38. 43. An article comprising anelectronically-accessible medium to provide access to instructions that,when executed, cause the one or more processors to: route signal linesand associated shield lines for an integrated circuit layout, whereinpower lines are not explicitly routed prior to routing the signal lines;identify one or more shield lines for use as power lines; and addadditional power lines to the layout explicitly if the shield linesidentified for use as power lines do not meet predetermined powerdelivery requirements.
 44. The article of claim 43 wherein theinstructions that cause the one or more processors to route signal linesand associated shield lines comprises instructions that, when executed,cause the one or more processors to dynamically determine an order forplacement based on geometric constraints, shielding constraints and/orpreviously routed signal and/or power lines.
 45. The article of claim 43wherein the instructions that cause the one or more processors to routesignal lines and associated shield lines comprise instructions that,when executed, cause the one or more processors to: place a selectedsignal line in a first available track, possibly adjacent to apreviously placed shield line and/or a previously placed power line; andplace a shield line, if necessary, adjacent to the placed selectedsignal line according to a predetermined policy of placing shield lineswithout an associated polarity.
 46. The article of claim 43 wherein theinstructions that cause the one or more processors to identify one ormore shield lines for use as power lines comprise instructions that,when executed, cause the one or more processors to: search a firstregion with respect to a first layout boundary for a shield line; causean identified shield line in first region, if any, to be a power line byassigning a polarity to the identified shield line; insert a power linein the first region if a shield line is not identified within the firstregion.
 47. The article of claim 46 further comprising instructionsthat, when executed, cause the one or more processors to: identify asecond region a predetermined distance beyond the first region; searchthe second region for a shield line; cause an identified shield line inthe second region, if any, to be a power line by assigning a polarity tothe identified shield line, wherein the polarity is opposite of theidentified shield line of the first region; insert a power line in thesecond region if a shield line is not identified within the secondregion.
 48. The article of claim 47 wherein the predetermined distancecorresponds to a power pitch distance.
 49. The article of claim 47wherein searching the second region for a shield line comprisesidentifying a shield line a greatest distance from the first region. 50.A method comprising: routing signal lines with associated shield linesfor an integrated circuit design block layout; extracting, from therouted shield lines, a power grid, if possible; and adding, explicitly,power lines to the integrated circuit design block layout to satisfypower delivery requirements explicitly if the shield lines identifiedfor use as power lines do not meet predetermined power deliveryrequirements.
 51. The method of claim 50 wherein extracting, from therouted shield lines, a power grid, if possible comprises: searching afirst region with respect to a first layout boundary for a shield line;and causing an identified shield line in first region, if any, to be apower line by assigning a polarity to the identified shield line. 52.The method of claim 51 further comprising: identifying a second region apredetermined distance beyond the first region; searching the secondregion for a shield line; and causing an identified shield line in thesecond region, if any, to be a power line by assigning a polarity to theidentified shield line, wherein the polarity is opposite of theidentified shield line of the first region; inserting a power line inthe second region if a shield line is not identified within the secondregion.
 53. An article comprising an electronically-accessible mediumthat provides instructions that, when executed, cause one or moreelectronic systems to: route signal lines with associated shield linesfor an integrated circuit design block layout; extract, from the routedshield lines, a power grid, if possible; and add, explicitly, powerlines to the integrated circuit design block layout to satisfy powerdelivery requirements explicitly if the shield lines identified for useas power lines do not meet predetermined power delivery requirements.54. The article of claim 53 wherein the instructions that cause the oneor more electronic systems to extract, from the routed shield lines, apower grid, if possible comprises instructions that, when executed,cause the one or more electronic systems to: search a first region withrespect to a first layout boundary for a shield line; and cause anidentified shield line in first region, if any, to be a power line byassigning a polarity to the identified shield line.
 55. The article ofclaim 54 further comprising instructions that, when executed, cause theone or more electronic systems to: identify a second region apredetermined distance beyond the first region; search the second regionfor a shield line; and cause an identified shield line in the secondregion, if any, to be a power line by assigning a polarity to theidentified shield line, wherein the polarity is opposite of theidentified shield line of the first region; insert a power line in thesecond region if a shield line is not identified within the secondregion.